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<title>MOVDDUP—Replicate Double FP Values </title></head>
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<h1>MOVDDUP—Replicate Double FP Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op / En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>F2 0F 12 /r MOVDDUP xmm1, xmm2/m64</td>
<td>RM</td>
<td>V/V</td>
<td>SSE3</td>
<td>Move double-precision floating-point value from xmm2/m64 and duplicate into xmm1.</td></tr>
<tr>
<td>VEX.128.F2.0F.WIG 12 /r VMOVDDUP xmm1, xmm2/m64</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Move double-precision floating-point value from xmm2/m64 and duplicate into xmm1.</td></tr>
<tr>
<td>VEX.256.F2.0F.WIG 12 /r VMOVDDUP ymm1, ymm2/m256</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Move even index double-precision floating-point values from ymm2/mem and duplicate each element into ymm1.</td></tr>
<tr>
<td>EVEX.128.F2.0F.W1 12 /r VMOVDDUP xmm1 {k1}{z}, xmm2/m64</td>
<td>DUP-RM</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move double-precision floating-point value from xmm2/m64 and duplicate each element into xmm1 subject to writemask k1.</td></tr>
<tr>
<td>EVEX.256.F2.0F.W1 12 /r VMOVDDUP ymm1 {k1}{z}, ymm2/m256</td>
<td>DUP-RM</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move even index double-precision floating-point values from ymm2/m256 and duplicate each element into ymm1 subject to writemask k1.</td></tr>
<tr>
<td>EVEX.512.F2.0F.W1 12 /r VMOVDDUP zmm1 {k1}{z}, zmm2/m512</td>
<td>DUP-RM</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move even index double-precision floating-point values from zmm2/m512 and duplicate each element into zmm1 subject to writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>DUP-RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>For 256-bit or higher versions: Duplicates even-indexed double-precision floating-point values from the source operand (the second operand) and into adjacent pair and store to the destination operand (the first operand).</p>
<p>For 128-bit versions: Duplicates the low double-precision floating-point value from the source operand (the second operand) and store to the destination operand (the first operand).</p>
<p>128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register are unchanged. The source operand is XMM register or a 64-bit memory location.</p>
<p>VEX.128 and EVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. The source operand is XMM register or a 64-bit memory location. The destination is updated conditionally under the writemask for EVEX version.</p>
<p>VEX.256 and EVEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed. The source operand is YMM register or a 256-bit memory location. The destination is updated conditionally under the writemask for EVEX version.</p>
<p>EVEX.512 encoded version: The destination is updated according to the writemask. The source operand is ZMM register or a 512-bit memory location.</p>
<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
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<h3>Figure 4-2.  VMOVDDUP Operation</h3>
<p><strong>Operation</strong></p>
<p><strong>VMOVDDUP (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>TMP_SRC[63:0] (cid:197) SRC[63:0]</p>
<p>TMP_SRC[127:64] (cid:197) SRC[63:0]</p>
<p>IF VL &gt;= 256</p>
<p>TMP_SRC[191:128] (cid:197) SRC[191:128]</p>
<p>TMP_SRC[255:192] (cid:197) SRC[191:128]</p>
<p>FI;</p>
<p>IF VL &gt;= 512</p>
<p>TMP_SRC[319:256] (cid:197) SRC[319:256]</p>
<p>TMP_SRC[383:320] (cid:197) SRC[319:256]</p>
<p>TMP_SRC[477:384] (cid:197) SRC[477:384]</p>
<p>TMP_SRC[511:484] (cid:197) SRC[477:384]</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197) TMP_SRC[i+63:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>; zeroing-masking</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VMOVDDUP (VEX.256 encoded version)</strong></p>
<p>DEST[63:0] (cid:197)SRC[63:0]</p>
<p>DEST[127:64] (cid:197)SRC[63:0]</p>
<p>DEST[191:128] (cid:197)SRC[191:128]</p>
<p>DEST[255:192] (cid:197)SRC[191:128]</p>
<p>DEST[MAX_VL-1:256] (cid:197)0</p>
<p><strong>VMOVDDUP (VEX.128 encoded version)</strong></p>
<p>DEST[63:0] (cid:197)SRC[63:0]</p>
<p>DEST[127:64] (cid:197)SRC[63:0]</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p><strong>MOVDDUP (128-bit Legacy SSE version)</strong></p>
<p>DEST[63:0] (cid:197)SRC[63:0]</p>
<p>DEST[127:64] (cid:197)SRC[63:0]</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VMOVDDUP __m512d _mm512_movedup_pd( __m512d a);</p>
<p>VMOVDDUP __m512d _mm512_mask_movedup_pd(__m512d s, __mmask8 k, __m512d a);</p>
<p>VMOVDDUP __m512d _mm512_maskz_movedup_pd( __mmask8 k, __m512d a);</p>
<p>VMOVDDUP __m256d _mm256_mask_movedup_pd(__m256d s, __mmask8 k, __m256d a);</p>
<p>VMOVDDUP __m256d _mm256_maskz_movedup_pd( __mmask8 k, __m256d a);</p>
<p>VMOVDDUP __m128d _mm_mask_movedup_pd(__m128d s, __mmask8 k, __m128d a);</p>
<p>VMOVDDUP __m128d _mm_maskz_movedup_pd( __mmask8 k, __m128d a);</p>
<p>MOVDDUP __m256d _mm256_movedup_pd (__m256d a);</p>
<p>MOVDDUP __m128d _mm_movedup_pd (__m128d a);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type 5;</p>
<table class="exception-table">
<tr>
<td>EVEX-encoded instruction, see Exceptions Type E5NF.</td></tr>
<tr>
<td>If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.</td></tr></table></body></html>